ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 69

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

ST72344xx ST72345xx
Note:
Note:
1
2
3
4
As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active
does not generate a reset. This means that the device cannot spend more than a defined
delay in this power saving mode.
Figure 30. Active-halt timing overview
Figure 31. Active-halt mode flowchart
This delay occurs only if the MCU exits Active-Halt mode by means of a reset.
Peripheral clocked with an external clock source can still be active.
Only the RTC interrupt and some specific interrupts can exit the MCU from Active-halt mode
(such as external interrupt). Refer to
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the
CC register are set to the current software priority level of the interrupt routine and restored
when the CC register is popped.
(Active-halt enabled)
Run
instruction
HALT
(AWUCSR.AWUEN=0)
HALT INSTRUCTION
N
(MCCSR.OIE=1)
Active-
Doc ID 12321 Rev 5
halt
INTERRUPT
Y
Table 17 on page 59
256 OR 4096 cycle
delay (after reset)
3)
interrupt
256 OR 4096 CPU CLOCK
Reset
OR SERVICE INTERRUPT
FETCH RESET VECTOR
or
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
N
CYCLE DELAY
RESET
Y
for more details.
2)
XX
XX
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
10
4)
4)
vector
Fetch
Run
Power-saving modes
69/247