ST72F264G2B6 STMicroelectronics, ST72F264G2B6 Datasheet - Page 103

MCU 8-BIT 8K FLASH 32-SDIP

ST72F264G2B6

Manufacturer Part Number
ST72F264G2B6
Description
MCU 8-BIT 8K FLASH 32-SDIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheets

Specifications of ST72F264G2B6

Mfg Application Notes
ST7 Checksum Capability, AN1070 App Note
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SDIP (0.400", 10.16mm)
Processor Series
ST72F2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7F264-IND/USB, ST72F34X-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
For Use With
497-6423 - BOARD EVAL BASED ON ST72264G1497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-5570

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11.6 I
11.6.1 Introduction
The I
tween the microcontroller and the serial I
provides both multimaster and slave functions,
and controls all I
tocol, arbitration and timing. It supports fast I
mode (400kHz).
11.6.2 Main Features
I
I
11.6.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
Figure 57. I
2
2
C Master Features:
C Slave Features:
Parallel-bus/I
Multi-master capability
7-bit/10-bit Addressing
SMBus V1.1 Compliant
Transmitter/Receiver flag
End-of-byte transmission flag
Transfer problem detection
Clock generation
I
Arbitration Lost Flag
End of byte transmission flag
Transmitter/Receiver Flag
Start bit detection flag
Start and Stop generation
Stop bit detection
I
Detection of misplaced start or stop condition
Programmable I
Transfer problem detection
End-of-byte transmission flag
Transmitter/Receiver flag
2
2
C bus busy flag
C bus busy flag
2
2
C Bus Interface serves as an interface be-
C BUS INTERFACE (I2C)
2
SCL
SDA
C BUS Protocol
2
C protocol converter
CONDITION
2
C bus-specific sequencing, pro-
2
START
C Address detection
MSB
1
2
C bus. It
2
2
C
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I
and a Fast I
ware.
Mode Selection
The interface can operate in the four following
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
Communication Flow
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to
ure
57.
ST72260Gx, ST72262Gx, ST72264Gx
8
2
C bus. This selection is made by soft-
ACK
9
CONDITION
STOP
VR02119B
103/172
2
C bus
Fig-
2
C

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