STR752FR2T6 STMicroelectronics, STR752FR2T6 Datasheet - Page 68

• Manufacturer Part Number: STR752FR2T6
• Description: MCU 32BIT 256KB FLASH 64-LQFP
• Manufacturer: STMicroelectronics
• Series: STR7r

Specifications of STR752FR2T6

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, SPI, SSI, SSP, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: STR752x
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SPI, SSI, SSP, USB
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, KSDK-STR750-PLUS, MCBSTR750, MCBSTR750U, MCBSTR750UME, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: STR750-MCKIT, STR750-SK/HIT, STR750-SK/IAR, STR750-SK/KEIL, STR750-SK/RAIS, STR750-EVAL, STX-PRO/RAIS, STX-RLINK, STR79-RVDK/CPP, STR79-RVDK, STR79-RVDK/UPG
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• For Use With: MCBSTR750UME - BOARD EVAL MCBSTR750 + ULINK-MEMCBSTR750U - BOARD EVAL MCBSTR750 + ULINK2497-5754 - KIT STARTER IAR STR750497-5753 - KIT STARTER KEIL FOR STR7/STR9497-5752 - KIT STARTER IAR FOR STR7/STR9497-5748 - BOARD EVALUATION FOR STR750XF497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5653

Electrical parameters
68/84
SMI - serial memory interface
Subject to general operating conditions with C
Table 40.
1. Data based on characterisation results, not tested in production.
2. Max. frequency = f
3. Valid for all temperature ranges: -40 to 105 °C, with 30 pF load capacitance.
4. Valid up to 60 °C, with 10 pF load capacitance.
Figure 39. SMI timing diagram
I
Subject to general operating conditions for V
The I
described in the following table with the restriction mentioned below:
2
t
t
t
t
t
v(SMI_DOUT)
h(SMI_DOUT)
C - Inter IC control interface
v(SMI_CSSx)
h(SMI_CSSx)
t
su(SMI_DIN)
t
t
h(SMI_DIN)
Symbol
r(SMI_CK)
f(SMI_CK)
f
SMI_CK
Restriction: The I/O pins which SDA and SCL are mapped to are not “True” Open-
Drain: when configured as open-drain, the PMOS connected between the I/O pin and
V
I/O pin and V
2
SMI_DIN
SMI_DOUT
SMI_CSSX
C interface meets the requirements of the Standard I
DD_IO
SMI_CK
INPUT
is disabled, but it is still present. Also, there is a protection diode between the
SMI characteristics
OUTPUT
OUTPUT
OUTPUT
SMI clock frequency
SMI clock rise time
SMI clock fall time
Data output valid time
Data output hold time
CSS output valid time
CSS output hold time
Data input setup time
Data input hold time
DD_IO
PCLK
/2 = 64/2 = 32 MHz.
. Consequently, when using this I
t
t
v(SMI_DOUT)
v(SMI_CSS)
t
su(SMI_DIN)
MSB OUT
Parameter
(1)
t
t
h(SMI_DOUT)
h(SMI_CSS)
t
MSB IN
h(SMI_DIN)
t
c(SMI_CK)
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
t
t
w(SMI_CKH)
w(SMI_CKL)
DD_IO
L
BIT6 OUT
≈
BIT6 IN
, f
30 pF.
PCLK
, and T
2
C in a multi-master network, it is
2
C communication protocol
A
unless otherwise specified.
t
t
r(SMI_CK)
f(SMI_CK)
Min
0
5
LSB OUT
LSB IN
32
48
Max
10
10
10
(2)(3)
8
0
0
(4)
Unit
MHz
ns