R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 113

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Table 12.3
ILVL2 to ILVL0 Bits
12.1.6.1
12.1.6.2
12.1.6.3
000b
001b
010b
100b
101b
011b
110b
111b
The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (enabled) enables the maskable
interrupt. Setting the I flag to 0 (disabled) disables all maskable interrupts.
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (=
interrupt not requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
Operations of the IR bit vary by Timer RD interrupt, clock synchronous serial I/O interrupt with chip select or
I
For details, refer to 12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts
and I
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrupt is acknowledged:
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. They do not affect one another.
2
C bus interface interrupt.
•
•
•
I flag = 1
IR bit = 1
Interrupt priority level > IPL
2
C bus Interface Interrupts (Interrupts with Multiple Interrupt Request Sources).
Settings of Interrupt Priority
Levels
I Flag
IR Bit
Bits ILVL2 to ILVL0 and IPL
Level 3
Level 6
Level 7
Level 0 (interrupt disabled)
Level 1
Level 2
Level 4
Level 5
Interrupt Priority Level
Page 95 of 458
Priority Order
High
Low
−
Table 12.4
000b
001b
010b
100b
101b
011b
110b
111b
IPL
IPL
Interrupt Priority Levels Enabled by
Interrupt level 1 and above
Interrupt level 2 and above
Interrupt level 3 and above
Interrupt level 4 and above
Interrupt level 5 and above
Interrupt level 6 and above
Interrupt level 7 and above
All maskable interrupts are disabled
Enabled Interrupt Priority Levels
12. Interrupts