R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 316

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 16.13
16.2.5.2
Figure 16.13 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Transmission (Clock Synchronous Communication Mode). During the data transmit, the clock synchronous
serial I/O with chip select operates as described below.
When the clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock
and data.
When the clock synchronous serial I/O with chip select is set as a slave device, it outputs data synchronized
with the input clock. When setting the TE bit to 1 (enables transmit) before writing the transmit data to the
SSTDR register, the TDRE bit is automatically set to 0 (data is not transferred from the SSTDR to SSTRSR
registers) and the data is transferred from the SSTDR to SSTRSR registers.
After the TDRE bit is set to 1 (data is transferred from the SSTDR to SSTRSR registers), a transmit is started.
When the TIE bit in the SSER register is set to 1, the TXI interrupt request is generated. When one frame of
data is transferred while the TDRE bit is set to 0, data is transferred from the SSTDR to SSTRSR registers and
a transmit of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set to 1, the TEND bit
in the SSSR register is set to 1 (the TDRE bit is set to 1 when the last bit of the transmit data is transmitted) and
the state is retained. The TEI interrupt request is generated when the TEIE bit in the SSER register is set to 1
(enables transmit-end interrupt request). The SSCK pin is retained “H” after transmit-end.
Transmit can not be performed while the ORER bit in the SSSR register is set to 1 (overrun error occurs).
Confirm that the ORER bit is set to 0 before transmit.
Figure 16.14 shows a Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode).
TDRE bit in
SSSR register
TEND bit in
SSSR register
• When SSUMS bit = 0 (clock synchronous communication mode), CPHS bit = 0 (data change
Process by
program
at odd numbers) and CPOS bit = 0 (“H” when clock stops)
Data Transmission
Transmission (Clock Synchronous Communication Mode)
Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
SSCK
SSO
1
0
1
0
Page 298 of 458
Write data to SSTDR register
TXI interrupt request generation
b0
b1
1 frame
b7
b0
TEI interrupt request
generation
16. Clock Synchronous Serial Interface
b1
1 frame
b7