R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 260

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 14.102 TRDOCR Register in PWM3 Mode
Timer RD Output Control Register
b7 b6 b5 b4 b3 b2
NOTES:
1.
2. When the pin functions are w aveform output (refer to Table 14.12 and 14.13) and the TRDOCR register is set, the
Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
stops).
initial output level is output.
b1 b0
Bit Symbol
TRDOCR
Symbol
TOA0
TOB0
TOC0
TOD0
TOA1
TOB1
TOC1
TOD1
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TRDIOA0 output level
selection bit
TRDIOB0 output level
selection bit
TRDIOC0 initial output level
selection bit
TRDIOD0 initial output level
selection bit
TRDIOA1 initial output level
selection bit
TRDIOB1 initial output level
selection bit
TRDIOC1 initial output level
selection bit
TRDIOD1 initial output level
selection bit
(1)
Address
Bit Name
013Dh
(2)
(2)
0 : Active level “H”,
1 : Active level “L”,
0 : Active level “H”,
1 : Active level “L”,
This bit is disabled in PWM3 mode.
initial output “L”,
output “H” by the compare match in the
TRDGRA1register,
output “L” by the compare match in the
TRDGRA0 register
initial output “H”,
output “L” by the compare match in the
TRDGRA1register,
output “H” by the compare match in the
TRDGRA0 register
initial output “L”,
output “H” by the compare match in the
TRDGRB1register,
output “L” by the compare match in the
TRDGRB0 register
initial output “H”,
output “L” by the compare match in the
TRDGRB1register,
output “H” by the compare match in the
TRDGRB0 register
After Reset
Function
00h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW