R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 130

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00
REJ09B0250-0200
12.6.5
Sample programs 1 to 3 are preventing the I flag from being set to 1 (interrupt enables) before changing the
interrupt control register for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag being set to 1 before interrupt control register is
Example 2: Use dummy read to have FSET instruction wait
Example 3: Use POPC instruction to change I flag
(a) Each interrupt control register can only be changed while interrupt requests corresponding to that
(b) When changing any interrupt control register after disabling interrupts, be careful with the instructions
(c) When disabling interrupts using the I flag, set the I flag according to the following sample programs.
INT_SWITCH1:
INT_SWITCH2:
INT_SWITCH3:
Aug 27, 2008
Changing Interrupt Control Register Contents
FCLR
AND.B
MOV.W
FSET
PUSHC
FCLR
AND.B
POPC
FCLR
AND.B
NOP
NOP
FSET
register are not generated. If interrupt requests may be generated, disable the interrupts before changing
the interrupt control register.
to be used.
When changing any bit other than IR bit
If an interrupt request corresponding to that register is generated while executing the instruction, the IR
bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register.
Instructions to use: AND, OR, BCLR, BSET
When changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction to be
used. Therefore, use the MOV instruction to set the IR bit to 0.
Refer to (b) for the change of interrupt control registers in the sample programs.
changed
I
I
I
I
I
FLG
#00H,0056H
#00H,0056H
MEM,R0
FLG
#00H,0056H
Page 112 of 458
; Disable interrupts
; Set TRAIC register to 00h
;
; Enable interrupts
; Disable interrupts
; Set TRAIC register to 00h
; Dummy read
; Enable interrupts
; Disable interrupts
; Set TRAIC register to 00h
; Enable interrupts
12. Interrupts