R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 301

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
16.2
Table 16.2
NOTE:
Transfer Data Format
Operating Mode
Master / Slave Device
I/O Pin
Transfer Clock
Receive Error Detection • Overrun error
Multimaster Error
Detection
Interrupt Request
Select Function
The serial data of the clock synchronous can communicate for the clock synchronous serial I/O with chip select.
Table 16.2 lists the Clock Synchronous Serial I/O with Chip Select Specifications and Figure 16.1 shows a Block
Diagram of Clock Synchronous Serial I/O with Chip Select.
Figures 16.2 to 16.9 show Clock Synchronous Serial I/O with Chip Select Associated Registers.
1. The interrupt vector table is one of the clock synchronous serial I/O with chip select specification.
Clock Synchronous Serial I/O with Chip Select (SSU)
Item
Clock Synchronous Serial I/O with Chip Select Specifications
Page 283 of 458
• Transfer-data length 8 bits
• Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
Selectable
SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip-select I/O pin
• When the MSS bit in the SSCRH register is set to 0 (operates as slave
• When the MSS bit in the SSCRH register is set to 1 (operates as master
• Clock polarity and phase of SSCK can be selected.
• Conflict error
5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,
overrun error and conflict error).
• Data transfer direction
• SSCK clock polarity
• SSCK clock phase
device), external clock can be selected.
device), internal clock (selects from f1/256, f1/128, f1/64, f1/32, f1/16, f1/8 and
f1/4 and outputs from SSCK pin) can be selected.
Continuous transmit and receive of serial data are enabled since both
transmitter and receiver have buffer structure.
Overrun error occurs during receive and completes by error. While the RDRF
bit in the SSSR register is set to 1 (data in the SSRDR register) and
completing the next serial data receive, the ORER bit is set to 1.
While the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode) and the MSS bit in the SSCRH register is set to 1
(operates as master device) and when starting a serial communication, the
CE bit in the SSSR register is set to 1 if “L” applies to the SCS pin input.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode), the MSS bit in the SSCRH register is set to 0
(operates as slave device) and the SCS pin input changes state from “L” to
“H”, the CE bit in the SSSR register is set to 1.
Selects MSB-first or LSB-first
Selects “L” or “H” level when clock stops
Selects edge of data change and data download
(1)
Specification
16. Clock Synchronous Serial Interface