R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 131

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
13. Watchdog Timer
The watchdog timer is a function to detect when the program is out of control. To use the watchdog timer is
recommend for improving reliability of a system. The watchdog timer contains a 15-bit counter and can select count
source protection mode is enabled or disabled.
Table 13.1 lists the Count Source Protection Mode
Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset.
Figure 13.1 shows the Block Diagram of Watchdog Timer, Figure 13.2 shows Registers OFS and WDC and Figure
13.3 shows Registers WDTR, WDTS, and CSPR.
Figure 13.1
Table 13.1
Count Source
Count Operation
Count Start Condition
Count Stop Condition
Reset Condition of Watchdog
Timer
Operation at the Time of
Underflow
CPU clock
Internal reset signal
NOTE:
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
Write to WDTR register
(“L” active)
Count Source Protection Mode
Block Diagram of Watchdog Timer
Item
Page 113 of 458
Prescaler
1/128
1/16
CPU clock
Decrement
Either of following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Stop mode, wait mode
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Watchdog timer interrupt or
watchdog timer reset
WDC7 = 1
WDC7 = 0
Count Source Protection
fOCO-S
Mode Disabled
CSPRO = 0
CSPRO = 1
Watchdog timer
Low-speed on-chip oscillator
clock
None
Watchdog timer reset
Count Source Protection
Set to
7FFFh
Mode Enabled
(1)
CSPRO: Bit in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
13. Watchdog Timer
PM12 = 0
Watchdog timer
interrupt request
PM12 = 1
Watchdog
timer reset