R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 212

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 14.56
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4
NOTES:
1.
2.
3. Including w hen the BFji bit (j = C or D) in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Nothing is assigned to the b5 in the TRDSR0 register. When w riting to the b5, w rite 0. When reading, its content is 1.
The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and w riting 0 to the same bit.
• This bit remains unchanged even if the read result is 0 and w riting 0 to the same bit. (This bit remains 1 even if this
• This bit remains unchanged w hen w riting 1.
bit is set to 1 from 0 after reading, and w riting 0.)
b3 b2
Registers TRDSR0 to TRDSR1 in Output Compare Function
b1 b0
Bit Symbol
(b7 - b6)
TRDSR0
TRDSR1
Symbol
Page 194 of 458
IMFA
IMFB
IMFC
IMFD
OVF
UDF
—
Input capture/compare match
flag A
Input capture/compare match
flag B
Input capture/compare match
flag C
Input capture/compare match
flag D
Overflow flag
Underflow flag
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Address
Bit Name
0143h
0153h
(1)
[Source for setting this bit to 0]
Write 0 after read.
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRAi register.
[Source for setting this bit to 0]
Write 0 after read.
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRBi register.
[Source for setting this bit to 0]
Write 0 after read.
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRCi register.
[Source for setting this bit to 0]
Write 0 after read.
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRDi register.
[Source for setting this bit to 0]
Write 0 after read.
[Source for setting this bit to 1]
When the TRDi register overflow s.
This bit is disabled in the output compare function.
(2)
(2)
(2)
(2)
(2)
After Reset
11100000b
11000000b
Function
(3)
(3)
14. Timers
RW
RW
RW
RW
RW
RW
RW
—