HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 115

MCU 5V 0K I-TEMP PB-FREE 112-QFP

HD6417034AFI20V

Manufacturer Part Number
HD6417034AFI20V
Description
MCU 5V 0K I-TEMP PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417034AFI20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417034AFI20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.2.2
The two break address mask registers—break address mask register H (BAMRH) and break
address mask register L (BARML)—together form a single group. Both are 16-bit read/write
registers. BAMRH determines which of the bits in the break address set in BARH are masked.
BAMRL determines which of the bits in the break address set in BARL are masked. A reset
initializes BAMRH and BARML to H'0000. They are not initialized in standby mode.
BAMRH: Break address mask register H.
BAMRH bits 15–0—Break Address Mask 31–16 (BAM31–BAM16): BAM31–BAM16 specify
whether bits BA31–BA16 of the break address set in BARH are masked or not.
BAMRL: Break address mask register L.
BAMRL bits 15–0—Break Address Mask 15–0 (BAM15–BAM0)): BAM15–BAM0 specify
whether bits BA15–BA0 of the break address set in BARH are masked or not.
Bits 15–0:
BAMn
0
1
n = 31–0
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Break Address Mask Register (BAMR)
Description
Break address bit BAn is included in the break condition
Break address bit BAn is not included in the break condition
BAM31
BAM23
BAM15
BAM7
R/W
R/W
R/W
R/W
15
15
0
7
0
0
7
0
BAM30
BAM22
BAM14
BAM6
R/W
R/W
R/W
R/W
14
14
0
6
0
0
6
0
BAM29
BAM21
BAM13
BAM5
R/W
R/W
R/W
R/W
13
13
0
5
0
0
5
0
BAM28
BAM20
BAM12
BAM4
R/W
R/W
R/W
R/W
12
12
0
4
0
0
4
0
Rev. 7.00 Jan 31, 2006 page 87 of 658
Section 6 User Break Controller (UBC)
BAM27
BAM19
BAM11
BAM3
R/W
R/W
R/W
R/W
11
11
0
3
0
0
3
0
BAM26
BAM18
BAM10
BAM2
R/W
R/W
R/W
R/W
10
10
0
2
0
0
2
0
REJ09B0272-0700
BAM25
BAM17
BAM9
BAM1
R/W
R/W
R/W
R/W
9
0
1
0
9
0
1
0
(Initial value)
BAM24
BAM16
BAM8
BAM0
R/W
R/W
R/W
R/W
8
0
0
0
8
0
0
0

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