HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 321

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.5.3
The ITU has compare match/input capture A interrupts, compare match/input capture B interrupts
and overflow interrupts for each channel. Each of the fifteen of these three types of interrupts are
allocated their own independently vectored addresses. When the interrupt's interrupt request flag is
set to 1 and the interrupt enable bit is set to 1, the interrupt is requested.
The channel priority order can be changed with the interrupt controller. For more information, see
section 5, Interrupt Controller (INTC). The compare match/input capture A interrupts of channels
0–3 can start the DMAC to transfer data. Table 10.17 lists the interrupt sources.
Table 10.17 ITU Interrupt Sources
Channel
0
1
2
3
4
Note: * Indicates the initial status following a reset. The ranking of channels can be altered using
the interrupt controller.
Interrupt Sources and DMAC Activation
Interrupt
Source
IMIA0
IMIB0
OVI0
IMIA1
IMIB1
OVI1
IMIA2
IMIB2
OVI2
IMIA3
IMIB3
OVI3
IMIA4
IMIB4
OVI4
Description
Compare match or input capture A0
Compare match or input capture B0
Overflow 0
Compare match or input capture A1
Compare match or input capture B1
Overflow 1
Compare match or input capture A2
Compare match or input capture B2
Overflow 2
Compare match or input capture A3
Compare match or input capture B3
Overflow 3
Compare match or input capture A4
Compare match or input capture B4
Overflow 4
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Rev. 7.00 Jan 31, 2006 page 293 of 658
DMAC
Activation
Yes
No
No
Yes
No
No
Yes
No
No
Yes
No
No
No
No
No
REJ09B0272-0700
Priority
Order *
High
Low