HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 173

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Bus State Controller (BSC)
8.5
DRAM Interface Operation
When the DRAM enable bit (DRAME) in BCR is set to 1, area 1 becomes DRAM space and the
DRAM interface function is available, which permits direct connection of this chip to DRAMs.
8.5.1
DRAM Address Multiplexing
When the multiplex enable bit (MXE) in the DRAM area control register (DCR) is set to 1, row
addresses and column addresses are multiplexed. This allows DRAMs that require multiplexing of
row and column addresses to be connected directly to an SH microprocessor without additional
multiplexing circuits. When addresses are multiplexed (MXE = 1), setting of the DCR’s multiplex
shift bits (MXC1, MXC0) allows selection of eight, nine and ten-bit row address shifting. Table
8.10 illustrates the relationship between the MXC1/MXC0 bits and address multiplexing.
Rev. 7.00 Jan 31, 2006 page 145 of 658
REJ09B0272-0700