HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 147

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 9 and 8—Multiplex Shift Count 1 and 0 (MXC1 and MXC0): Shift row addresses
downward by a certain number of bits (8–10) when row and column addresses are multiplexed
(MXE = 1). Regardless of the MXE bit setting, these bits also select the range of row addresses
compared in burst operation.
Bit 9:
MXC1
0
1
Bits 7–0—Reserved: These bits are always read as 0. The write value should always be 0.
8.2.6
The refresh control register (RCR) is a 16-bit read/write register that controls the start of refresh-
ing and selects the refresh mode and the number of wait states during refreshing. It is initialized to
H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
To prevent RCR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'5A is written in the upper byte, and the
actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
Bit 15–8—Reserved: These bits are always read as 0.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Refresh Control Register (RCR)
Bit 8:
MXC0
0
1
0
1
RFSHE RMODE
Row Address Shift
(MXE = 1)
8 bits
9 bits
10 bits
Reserved
R/W
15
—
—
0
7
0
R/W
14
—
—
(Initial value)
0
6
0
RLW1
R/W
13
—
—
0
5
0
RLW0
R/W
12
Row Address Bits Compared
(in Burst Operation) (MXE = 0 or 1)
A8–A27
A9–A27
A10–A27
Reserved
—
—
0
4
0
Rev. 7.00 Jan 31, 2006 page 119 of 658
Section 8 Bus State Controller (BSC)
11
—
—
—
—
0
3
0
10
—
—
—
—
0
2
0
REJ09B0272-0700
—
—
—
—
9
0
1
0
(Initial value)
—
—
—
—
8
0
0
0