HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 371

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 5—Timer Enable (TME): TME enables or disables the timer.
Bit 5: TME
0
1
Bits 4 and 3—Reserved): These bits are always read as 1. The write value should always be 1.
Bits 2–0—Clock Select 2–0 (CKS2–CKS0): CKS2–CKS0 select one of eight internal clock
sources for input to TCNT. The clock signals are obtained by dividing the frequency of the system
clock ( ).
Bit 2: CKS2 Bit 1: CKS1
0
0
0
0
1
1
1
1
Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an
12.2.3
RSTCSR is an eight-bit read/write register that controls output of the reset signal generated by
timer counter (TCNT) overflow and selects the internal reset signal type. RSTCSR differs from
other registers in that it is more difficult to write. See section 12.2.4, Notes on Register Access, for
details. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not
initialized by the internal reset signal generated by overflow of the WDT. It is initialized to H'1F
in standby mode.
overflow occurs.
Reset Control/Status Register (RSTCSR)
0
0
1
1
0
0
1
1
Description
Timer disabled: TCNT is initialized to H'00 and count-up stops
Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is
generated when TCNT overflows.
Bit 0: CKS0
0
1
0
1
0
1
0
1
Clock Source
/2 (Initial value)
/64
/128
/256
/512
/1024
/4096
/8192
Rev. 7.00 Jan 31, 2006 page 343 of 658
Section 12 Watchdog Timer (WDT)
Overflow Interval * ( = 20 MHz)
25.6 µs
819.2 µs
1.6 ms
3.3 ms
6.6 ms
13.1 ms
52.4 ms
104.9 ms
Description
(Initial value)
REJ09B0272-0700