HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 82

MCU 5V 0K I-TEMP PB-FREE 112-QFP

HD6417034AFI20V

Manufacturer Part Number
HD6417034AFI20V
Description
MCU 5V 0K I-TEMP PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417034AFI20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417034AFI20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 4 Exception Handling
4.1.3
Exception Vector Table
Before exception handling can execute, the exception vector table must be set in memory. The
exception vector table holds the start addresses of exception handling routines (the table for reset
exception handling stores initial PC and SP values). Different vector numbers and vector table
address offsets are assigned to different exception sources. The vector table addresses are
calculated from the corresponding vector numbers and vector address offsets. In exception
handling, the exception handling routine start address is fetched from the exception vector table
indicated by this vector table address.
Table 4.2 lists vector numbers and vector table address offsets. Table 4.3 shows how vector table
addresses are calculated.
Rev. 7.00 Jan 31, 2006 page 54 of 658
REJ09BX0272-0700

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