HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 416

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 Serial Communication Interface (SCI)
In receiving, the SCI operates as follows:
1. The SCI monitors the receive data line. When it detects a start bit (0), the SCI synchronizes
2. Receive data is shifted into RSR in order from the LSB to the MSB.
3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following
2.
Figure 13.8 shows an example of SCI receive operation in asynchronous mode.
Table 13.11 Receive Error Conditions and SCI Operation
Receive Error
Overrun error
Framing error
Parity error
Rev. 7.00 Jan 31, 2006 page 388 of 658
REJ09B0272-0700
internally and starts receiving.
checks:
a. Parity check: The number of 1s in the receive data must match the even or odd parity
b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit
c. Status check: RDRF must be 0 so that receive data can be loaded from RSR into RDR.
Note:
After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR,
the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or
FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCR is also set to 1, the
SCI requests a receive-error interrupt (ERI).
setting of the O/E bit in SMR.
is checked.
If these checks all pass, the SCI sets RDRF to 1 and stores the received data in RDR. If one
of the checks fails (receive error), the SCI operates as indicated in table 13.11.
When a receive error flag is set, further receiving is disabled. The RDRF bit is not
set to 1. Be sure to clear the error flags.
Abbreviation
ORER
FER
PER
Condition
RDRF is still set to 1 in SSR
Stop bit is 0
even/odd parity setting in SMR
Receiving of next data ends while
Parity of receive data differs from
Data Transfer
Receive data not loaded
from RSR into RDR
Receive data loaded from
RSR into RDR
Receive data loaded from
RSR into RDR