HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 308

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
GR Setting in Complementary PWM Mode: Note the following when setting the general
registers in complementary PWM mode and when making changes during operation.
Buffer Transfers when Changing from Increment to Decrement: When the contents of GR are
in the range GRA3 – T + 1 to GRA3, do not transfer a value outside this range. When the contents
of GR are outside this range, do not a transfer a value within it. Figure 10.39 illustrates a point for
caution regarding changing of GR settings with buffer operation.
Buffer Transfers when Changing from Decrement to Increment: When the contents of GR are
in the range H'0000 to T–1, do not transfer a value outside this range. When the contents of GR
are outside this range, do not transfer a value within it. Figure 10.40 illustrates this point for
caution regarding changing of GR settings with buffer operation
Rev. 7.00 Jan 31, 2006 page 280 of 658
REJ09B0272-0700
Initial values: Settings from H'0000 to T–1 (T: TCNT3 initial setting) are prohibited. After
counting starts, this setting is allowed from the point when the first A3 compare match occurs.
Methods of changing settings: Use buffer operation. Writing directly to general registers may
result in incorrect waveform output.
When changing settings: See figure 10.38.
GRA3 – T + 1
H' 0000
Figure 10.38 Example of Changing GR Settings with Buffer Operation (1)
Figure 10.39 Caution on Changing GR Settings with Buffer Operation (1)
GRA3
GRA3 – T
GRA3 + 1
GR
GR
BR
GRA3
Changes prohibited
Prohibited
TCNT3
TCNT4