HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 130

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Interrupt Controller
5.2.3
ISR is an 8-bit readable/writable register that indicates the status of IRQ
requests.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 0.
Bits 5 to 0—IRQ
IRQ
Bits 5 to 0:
IRQ5F to IRQ0F
0
1
Note: n = 5 to 0
Rev. 3.00 Sep 27, 2006 page 102 of 872
REJ09B0325-0300
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear flags.
0
interrupt requests.
IRQ Status Register (ISR)
5
to IRQ
Reserved bits
Description
[Clearing conditions]
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
7
0
0
Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ
6
0
IRQ5F
R/(W) *
5
0
IRQ4F
R/(W) *
4
0
IRQ to IRQ flags
These bits indicate IRQ to IRQ
interrupt request status
IRQ3F
R/(W) *
3
0
5
IRQ2F
R/(W) *
0
2
0
0
to IRQ
IRQ1F
R/(W) *
5
5
1
0
interrupt
(Initial value)
IRQ0F
R/(W) *
0
0
0
5
to