HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 266

IC H8 MCU FLASH 128K 100QFP

HD64F3048F16

Manufacturer Part Number
HD64F3048F16
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of HD64F3048F16

Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Package
100PQFP
Family Name
H8
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
70
Interface Type
SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3048F16
Manufacturer:
RENESAS
Quantity:
1
Part Number:
HD64F3048F16
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3048F16
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD64F3048F16
Manufacturer:
RENESAS
Quantity:
20 000
Part Number:
HD64F3048F16V
Manufacturer:
SIEMENS
Quantity:
200
Part Number:
HD64F3048F16V
Manufacturer:
RENESAS
Quantity:
5 530
Part Number:
HD64F3048F16V
Manufacturer:
RENESAS
Quantity:
3 477
Part Number:
HD64F3048F16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 8 DMA Controller
Figure 8.12 shows a sample setup procedure for block transfer mode.
Rev. 3.00 Sep 27, 2006 page 238 of 872
REJ09B0325-0300
Note: Carry out settings 1 to 10 with the DEND interrupt masked in the CPU.
Set block transfer count
Set destination address
Block transfer mode
Block transfer mode
Set source address
If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in
which case the transfer will not start.
Set DTCRB (1)
Set DTCRA (1)
Set DTCRB (2)
Set DTCRA (2)
Set block size
Read DTCRB
Read DTCRA
Figure 8.12 Block Transfer Mode Setup Procedure (Example)
1
2
3
4
5
6
7
8
9
10
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Set the source address in MARA.
Set the destination address in MARB.
Set the block transfer count in ETCRB.
Set the block size (number of bytes or words)
in both ETCRAH and ETCRAL.
Set the DTCRB bits as follows.
Set the DTCRA bits as follows.
Read DTCRB with DTME cleared to 0.
Set the DTME bit to 1 in DTCRB.
Read DTCRA with DTE cleared to 0.
Set the DTE bit to 1 in DTCRA to enable
the transfer.
Clear the DTME bit to 0.
Set the DAID and DAIDE bits to select whether
MARB is incremented, decremented, or held fixed.
Set or clear the TMS bit to make the block area
the source or destination.
Select the DMAC activation source with bits
DTS2B to DTS0B.
Clear the DTE to 0.
Select byte size or word size with the DTSZ bit.
Set the SAID and SAIDE bits to select whether
MARA is incremented, decremented, or held fixed.
Set or clear the DTIE bit to enable or disable the
CPU interrupt at the end of the transfer.
Set bits DTS2A to DTS0A all to 1 to select
block transfer mode.

Related parts for HD64F3048F16