HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 374

IC H8 MCU FLASH 128K 100QFP

HD64F3048F16

Manufacturer Part Number
HD64F3048F16
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of HD64F3048F16

Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Package
100PQFP
Family Name
H8
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
70
Interface Type
SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 10 16-Bit Integrated Timer Unit (ITU)
Bits 6 and 5—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how TCNT is
cleared.
Bit 6: CCLR1
0
1
Notes: 1. TCNT is cleared by compare match when the general register functions as an output
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input
edges when an external clock source is used.
Bit 4: CKEG1
0
1
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.
Phase counting takes precedence.
Rev. 3.00 Sep 27, 2006 page 346 of 872
REJ09B0325-0300
2. Selected in TSNC.
compare register, and by input capture when the general register functions as an input
capture register.
Bit 5: CCLR0
0
1
0
1
Bit 3: CKEG0
0
1
Description
TCNT is not cleared
TCNT is cleared by GRA compare match or input
capture *
TCNT is cleared by GRB compare match or input
capture *
Synchronous clear: TCNT is cleared in synchronization
with other synchronized timers *
Description
Count rising edges
Count falling edges
Count both edges
1
1
2
(Initial value)
(Initial value)

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