HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 449

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.2.5
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP
TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of
NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or
different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1
If TPC output groups 0 and 1 are triggered by the same compare match event, the NDRA address
is H'FFA5. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FFA7
consists entirely of reserved bits that cannot be modified and are always read as 1.
Address H'FFA5
Address H'FFA7
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Next Data Register A (NDRA)
7
to TP
NDR7
R/W
0
7
0
7
1
). During TPC output, when an ITU compare match event specified in
Next data 7 to 4
These bits store the next output
data for TPC output group 1
NDR6
R/W
6
0
6
1
NDR5
R/W
5
0
5
1
Section 11 Programmable Timing Pattern Controller
NDR4
Reserved bits
R/W
4
0
4
1
Rev. 3.00 Sep 27, 2006 page 421 of 872
NDR3
R/W
3
0
3
1
Next data 3 to 0
These bits store the next output
data for TPC output group 0
NDR2
R/W
2
0
2
1
REJ09B0325-0300
NDR1
R/W
1
1
1
0
NDR0
R/W
0
0
0
1