HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 249

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Repeat Mode
One byte or word is transferred per request. A designated number of these transfers are executed.
When the designated number of transfers are completed, the initial address and counter value are
restored and operation continues. No CPU interrupt is requested. One 24-bit address and one 8-bit
address are specified. The transfer direction is determined automatically from the activation
source.
Normal Mode
Auto-request: The DMAC is activated by register setup alone, and continues executing transfers
until the designated number of transfers have been completed. A CPU interrupt can be requested at
completion of the transfers. Both addresses are 24-bit addresses.
External request: One byte or word is transferred per request. A designated number of these
transfers are executed. A CPU interrupt can be requested at completion of the designated number
of transfers. Both addresses are 24-bit addresses.
Block Transfer Mode
One block of a specified size is transferred per request. A designated number of block transfers are
executed. At the end of each block transfer, one address is restored to its initial value. When the
designated number of blocks have been transferred, a CPU interrupt can be requested. Both
addresses are 24-bit addresses.
Cycle-steal mode
The bus is released to another bus master after each byte or word is transferred.
Burst mode
Unless requested by a higher-priority bus master, the bus is not released until the designated
number of transfers have been completed.
Rev. 3.00 Sep 27, 2006 page 221 of 872
Section 8 DMA Controller
REJ09B0325-0300