HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 522

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 13 Serial Communication Interface
Transmitting and Receiving Data
Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for
transmitting multiprocessor serial data and indicates the procedure to follow.
Rev. 3.00 Sep 27, 2006 page 494 of 872
REJ09B0325-0300
Clear DR bit to 0, set DDR bit to 1
TDR and set MPBT bit in SSR
Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit to 0 in SCR
Write transmit data in
Clear TDRE flag to 0
Output break signal?
All data transmitted?
Start transmitting
TDRE = 1?
TEND = 1?
Initialize
End
Yes
Yes
Yes
Yes
No
No
No
No
1
2
3
4
1.
2.
3.
4.
SCI initialization: the transmit data
output function of the TxD pin is
selected automatically.
SCI status check and transmit data
write: read SSR, check that the TDRE
flag is 1, then write transmit
data in TDR. Also set the MPBT flag to
0 or 1 in SSR. Finally, clear the TDRE
flag to 0.
To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be
written, write data in TDR, then clear
the TDRE flag to 0. When the DMAC
is activated by a transmit-data-empty
interrupt request (TXI) to write data in
TDR, the TDRE flag is checked and
cleared automatically.
To output a break signal at the end of
serial transmission: set the DDR bit to
1 and clear the DR bit to 0 (DDR and
DR are I/O port registers), then clear
the TE bit to 0 in SCR.