HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 154

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller
6.1.4
Table 6.2 summarizes the bus controller’s registers.
Table 6.2
Address *
H'FFEC
H'FFED
H'FFEE
H'FFEF
H'FFF3
H'FF5F
Note:
6.2
6.2.1
ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.
When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus
mode: the upper data bus (D
bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus (D
D
mode. In modes 2, 4, and 7 ABWCR is initialized to H'00 by a reset and in hardware standby
mode. ABWCR is not initialized in software standby mode.
Rev. 3.00 Sep 27, 2006 page 126 of 872
REJ09B0325-0300
Bit
Initial
value
Read/Write
0
). In modes 1, 3, 5, and 6 ABWCR is initialized to H'FF by a reset and in hardware standby
Modes 1, 3, 5, 6
Modes 2, 4, 7
* Lower 16 bits of the address.
Register Configuration
Register Descriptions
Bus Width Control Register (ABWCR)
Bus Controller Registers
Name
Bus width control register
Access state control register
Wait control register
Wait state controller enable
register
Bus release control register
Chip select control register
ABW7
R/W
7
1
0
15
to D
ABW6
R/W
6
1
0
8
) is valid, and port 4 is an input/output port. When at least one
Bits selecting bus width for each area
ABW5
R/W
5
1
0
ABWCR
BRCR
Abbreviation
ASTCR
WCR
WCER
CSCR
ABW4
R/W
4
1
0
ABW3
R/W
3
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ABW2
R/W
2
1
0
H'F3
Modes
1, 3, 5, 6
H'FF
H'FF
H'FF
H'FE
H'0F
Initial Value
ABW1
R/W
1
1
0
Modes
2, 4, 7
H'00
H'FF
H'F3
H'FF
H'FE
H'0F
ABW0
R/W
0
1
0
15
to