HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 128

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3.3.4
In addition to the SH and SZ bits, the page management information of TLB entries also includes
D, C, and PR bits.
The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit
is 0, an attempt to write to the page results in an initial page write exception. For physical page
swapping between secondary memory and main memory, for example, pages are controlled so that
a dirty page is paged out of main memory only after that page is written back to secondary
memory. To record that there has been a write to a given page in the address translation table in
memory, an initial page write exception is used.
The C bit in the entry indicates whether the referenced page resides in a cacheable or non-
cacheable area of memory. When the on-chip module control registers in area 1 are mapped, set
the C bit to 0. The PR field specifies the access rights for the page in privileged and user modes
and is used to protect memory. Attempts at non-permitted accesses result in TLB protection
violation exceptions.
Access states designated by the D, C, and PR bits are shown in table 3.1.
Table 3.1
D bit
C bit
PR bit
Rev. 2.00, 09/03, page 80 of 690
Page Management Information
0
1
0
1
00
01
10
11
Access States Designated by D, C, and PR Bits
Reading
Permitted
Permitted
Permitted
(no caching)
Permitted
(with caching)
Permitted
Permitted
Permitted
Permitted
Privileged Mode
Writing
Initial page write
exception
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation exception
Permitted
TLB protection
violation exception
Permitted
Reading
Permitted
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation
exception
TLB protection
violation
exception
Permitted
Permitted
User Mode
Writing
Initial page write
exception
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation exception
TLB protection
violation exception
TLB protection
violation exception
Permitted