HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 474

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

16.5
SCIF Interrupt Sources and DMAC
The SCIF supports six interrupts in asynchronous mode—transmit-FIFO-data-empty (TXI),
transmit-data-stop (TDI), receive-error (ERI), receive-FIFO-data-full (RXI), break-receive (BRI),
and receive-data-ready (DRI). The vectors of transmit-data-stop and transmit-FIFO-data-empty
interrupts are the same. The vectors of receive-error and break-receive interrupts are the same. The
vectors of receive-FIFO-data-full and receive-data-ready interrupts are the same.
In clock synchronous mode, the SCIF supports two interrupts—transmit-FIFO-data-empty (TXI)
and receive-FIFO-data-full (RXI).
Table 16.4 shows the interrupt sources. The interrupt sources can be enabled or disabled by means
of the TIE, RIE, ERIE, BRIE, DRIE, and TSIE bits in SCSCR.
When the TDFE flag in SCSSR is set to 1, a TXI interrupt request is generated. When the TSF
flag in SCSSR is set to 1, a TDI interrupt request is generated. The DMAC can be activated and
data transfer performed on generation of TXI and TDI interrupt requests. The DMAC requests of
TXI and TDI are assigned to the same vector.
When the RDF flag in SCSSR is set to 1, an RXI interrupt request is generated. The DMAC can
be activated and data transfer performed on generation of an RXI interrupt request.
When using the DMAC for transmission/reception, set and enable the DMAC before making SCIF
settings. See section 8, Direct Memory Access Controller (DMAC), for details of the DMAC
setting procedure.
When the ER flag in SCSSR is set to 1, an ERI interrupt request is generated. When the BRK flag
in SCSSR is set to 1, a BRI interrupt request is generated. When the DR flag in SCSSR is set to 1,
a DRI interrupt request is generated. When the TSF flag in SCSSR is set to 1, a TDI interrupt
request is generated.
The vectors of TXI and TDI, ERI and BRI, and RXI and DRI are the same.
The DMAC activation and interrupts cannot be generated simultaneously by the same source. The
following procedure should be used for the DMAC activation.
1. Set the interrupt enable bits (TIE and RIE) corresponding to the generated source to 1.
2. Mask the corresponding interrupt requests by using the interrupt mask register of the interrupt
controller.
Rev. 2.00, 09/03, page 426 of 690