HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 556

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

20.1.2
PADR is an 8-bit readable/writable register that stores data for pins PTA7 to PTA0. Bits PA7DT
to PA0DT correspond to pins PTA7 to PTA0. When the pin function is general output port, if the
port is read, the value of the corresponding PADR bit is returned directly. When the function is
general input port, if the port is read the corresponding pin level is read.
Table 20.1 Port A Data Register (PADR) Read/Write Operations
PAnMD1 PAnMD0 Pin State
0
1
Note: n = 0 to 7
20.2
Port B is an 8-bit input/output port with the pin configuration shown in figure 20.2. Each pin has
an input pull-up MOS, which is controlled by the port B control register (PBCR) in the PFC.
Rev. 2.00, 09/03, page 508 of 690
Bit
7 to 0
PACR State
Port A Data Register (PADR)
Port B
Bit
Name
PA7DT
to
PA0DT
0
1
0
1
Other function PADR value
Output
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
Initial
Value
0
Port B
R/W
R/W
PTB7 (input/output)/D31 (input/output)/PINT15 (input)
PTB6 (input/output)/D30 (input/output)/PINT14 (input)
PTB5 (input/output)/D29 (input/output)/PINT13 (input)
PTB4 (input/output)/D28 (input/output)/PINT12 (input)
PTB3 (input/output)/D27 (input/output)/PINT11 (input)
PTB2 (input/output)/D26 (input/output)/PINT10 (input)
PTB1 (input/output)/D25 (input/output)/PINT9 (input)
PTB0 (input/output)/D24 (input/output)/PINT8 (input)
Read
PADR value
Pin state
Pin state
Figure 20.2 Port B
Description
Table 20.1 shows the function of PADR.
Write
Data can be written to PADR but no effect on
pin state.
Written data is output from the pin.
Data can be written to PADR but no effect on
pin state.
Data can be written to PADR but no effect on
pin state.