HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 169

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

DMA Address Error:
5.3.3
When the address translation unit of the memory management unit (MMU) is valid, MMU
exceptions are checked after a CPU address error has been checked. Four types of MMU
exceptions are defined: TLP error exception, TLP invalid exception, TLB protection exception,
and initial page write exception. These exceptions are checked in this order.
A vector offset for a TLB error exception is defined as H'00000400 to simplify exception source
determination. For details on MMU exception operations, refer to section 3, Memory Management
Unit (MMU).
TLB Miss Exception:
Remarks
For details on user break controller, refer to section 22, User Break Controller (UBC).
Conditions
Types
Instruction asynchronous, processing-completion type
Save address
An address of the instruction following the instruction where a break occurs (a delayed branch
instruction destination address if an instruction is assigned to a delay slot)
Exception code
H'5C0
Remarks
An exception occurs when a DMA transfer is executed while an illegal instruction address
described above is specified in the DMAC. Since the DMA transfer is performed
asynchronously with the CPU instruction operation, an exception is also requested
asynchronously with the instruction execution. For details on DMAC, refer to section 8, Direct
Memory Access Controller (DMAC).
Conditions
Comparison of TLB addresses shows no address match.
Types
Instruction synchronous, re-execution type
Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n +
3)
General Exceptions (MMU Exceptions)
Rev. 2.00, 09/03, page 121 of 690