HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 395

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Example of Buffer Operation Setting Procedure: Figure 14.9 shows an example of the buffer
operation setting procedure.
Example of Buffer Operation
Figure 14.10 shows an operation example in which PWM mode has been designated for channel 0,
and buffer operation has been designated for TGRA and TGRC. The settings used in this example
are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at counter
clearing. Rewriting timing from the buffer register is set at counter clearing.
As buffer operation has been set, when compare match A occurs the output changes. When
counter clearing occurs by TGRB, the output changes and the value in buffer register TGRC is
simultaneously transferred to timer general register TGRA. This operation is repeated each time
compare match A occurs.
For details of PWM modes, see section 14.4.4, PWM Modes.
Set external pin function
Figure 14.9 Example of Buffer Operation Setting Procedure
Set buffer operation
Set rewriting timing
<Buffer operation>
Buffer operation
Start count
[1]
[2]
[3]
[4]
[1] Designate TGR for buffer operation with bits
[2] Set rewriting timing from the buffer register with
[3] Set the external pin function in pin function
[4] Set the CST bit in TSTR to 1 to start the count
BFA and BFB in TMDR.
bit BFWT in TMDR.
controller (PFC).
operation.
Rev. 2.00, 09/03, page 347 of 690