HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 489

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18.3.1
IFR0, together with interrupt flag register 1 (IFR1), indicates interrupt status information required
by the application. When an interrupt source is generated, the corresponding bit is set to 1 and an
interrupt request is sent to the CPU according to the combination with interrupt enable register 0
(IER0). Clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits.
However, EP1FULL and EP2EMPTY are status bits, and cannot be cleared.
Bit
7
6
5
4
3
2
Bit Name
BRST
EP1FULL
EP2TR
EP2EMPTY
SETUPTS
EP0oTS
Interrupt Flag Register 0 (IFR0)
Initial
Value
0
0
0
1
0
0
R/W
R/W
R
R/W
R
R/W
R/W
Description
Bus Reset
This bit is set to 1 when a bus reset signal is detected on
the USB bus.
EP1 FIFO Full
This bit is set when endpoint 1 receives one packet of
data successfully from the host, and holds a value of 1 as
long as there is valid data in the FIFO buffer.
This is a status bit, and cannot be cleared.
EP2 Transfer Request
This bit is set if there is no valid transmit data in the FIFO
buffer when an IN token for endpoint 2 is received from
the host. A NACK handshake is returned to the host until
data is written to the FIFO buffer and packet transmission
is enabled.
EP2 FIFO Empty
This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be
written.
This is a status bit, and cannot be cleared.
Setup Command Receive Complete
This bit is set to 1 when endpoint 0 receives successfully
a setup command requiring decoding on the application
side, and returns an ACK handshake to the host.
EP0o Receive Complete
This bit is set to 1 when endpoint 0 receives data from the
host successfully, stores the data in the FIFO buffer, and
returns an ACK handshake to the host.
Rev. 2.00, 09/03, page 441 of 690