HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 222

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
6, 5
4
3
2
1
0
Note:
7.4.4
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
The bits other than RFSH and RMODE should be written in the initialization after a power-on
reset and should not be modified after the initialization. When modifying these bits RFSH and
RMODE, do not change the values of other bits and write the previous values. Do not access area
2 or 3 until the SDCR register setting is complete when using synchronous DRAM.
Rev. 2.00, 09/03, page 174 of 690
*
Bit
Name
TRWL1
TRWL0
TRC1
TRC0
SDRAM Control Register (SDCR)
Specify area 3 as SDRAM when only one area is connected with SDRAM. In this case,
specify area 2 as normal space.
Initial
Value
0
0
0
0
0
0
R/W
R
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Cycles from WRITA/WRIT Command to Auto-
precharge/PRE Command
Specifies the number of cycles from issuing WRITA/WRIT
command to the start of auto-precharge or to issuing PRE
command. The setting for areas 2 and 3 is common.
00: 0 cycle
01: 1 cycle
10: 2 cycles
11: Setting prohibited
Reserved
This bit is always read as 0. The write value should always be
0.
Number of Cycles from REF Command/Self-refresh Release
to ACTV Command
Specify the number of cycles from issuing the REF command
or releasing self-refresh to issuing the ACTV command. The
setting for areas 2 and 3 is common.
00: 3 cycles
01: 4 cycles
10: 6 cycles
11: 9 cycles