HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 313

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

b. Burst Mode
Once the bus right is obtained, the transfer is performed continuously until the transfer end
condition is satisfied. In external request mode with low level detection of the DREQ pin,
however, when the DREQ pin is driven high, the bus passes to the other bus master after the
DMAC transfer request that has already been accepted ends, even if the transfer end conditions
have not been satisfied.
Burst mode cannot be used for other than the CMT when the on-chip peripheral module is the
transfer request source. Figure 8.11 shows DMA transfer timing in burst mode.
Figure 8.10 shows an example of DMA transfer timing in cycle steal intermittent mode.
Transfer conditions shown in the figure are:
Dual address mode
DREQ low level detection
Figure 8.10 Example of DMA Transfer in Cycle Steal Intermittent Mode
Bus cycle
Bus cycle
DREQ
DREQ
Figure 8.11 DMA Transfer Example in Burst Mode
CPU
CPU
(Dual Address, DREQ Low Level Detection)
(Dual Address, DREQ Low Level Detection)
CPU
CPU
CPU
CPU
DMAC DMAC CPU
Read/Write
DMAC DMAC DMAC
Read
Write
More than 16 or 64 Bφ
(change by the CPU's condition of using bus)
Read
DMAC DMAC
Write
CPU DMAC DMAC CPU
Rev. 2.00, 09/03, page 265 of 690
Read
Read/Write
DMAC
Write
CPU