HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 483

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

17.4.3
Received 3/16 IR frame bit-width pulses are demodulated and converted to a UART frame, as
shown in figure 17.2.
Demodulation to 0 is performed for pulse output, and demodulation to 1 is performed for no pulse
output.
17.4.4
The data format of UART frames used for IrDA communication must be specified by the SCIF0
registers. The UART frame has eight data bits, no parity bit, and one stop bit.
IrDA communication is performed in asynchronous mode, and this mode must also be specified
by the SCIF0 registers. The sampling rate must be set to 1/16.
The internal clock must be selected for the SCIF0 operation clock and the SCK0 pin must be
specified for the synchronizing clock output pin.
The IrDA communication rate is the same as the SCIF0 bit rate, which is specified by the SCIF0
registers.
For details on SCIF0 registers, refer to section 16, Serial Communication Interface with FIFO
(SCIF).
IR frame
Receiving
UART frame
Data Format Specification
Start bit
Start bit
Bit cycle
0
Transmit
Figure 17.2 Transmit/Receive Operation
0
1
1
0
0
UART frame
1
1
IR frame
0
3/16-bit cycle
pulse width
0
0
Data
Data
0
Receive
1
1
1
1
Rev. 2.00, 09/03, page 435 of 690
0
0
1
1
Stop bit
Stop bit