HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 508

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5. Status Stage (Control-Out)
The control-out status stage starts with an IN token from the host. When an IN-token is received at
the start of the status stage, there is not yet any data in the EP0i FIFO, and so an EP0i transfer
request interrupt is generated. The application recognizes from this interrupt that the status stage
has started. Next, in order to transmit 0-byte data to the host, 1 is written to the EP0i packet enable
bit but no data is written to the EP0i FIFO. As a result, the next IN token causes 0-byte data to be
transmitted to the host, and control transfer ends.
After the application has finished all processing relating to the data stage, 1 should be written to
the EP0i packet enable bit.
Rev. 2.00, 09/03, page 460 of 690
0-byte transmission to host
Set EP0i transmission
End of control transfer
(IFR0.EP0i TS = 1)
IN token reception
Figure 18.9 Status Stage (Control-Out) Operation
in EP0i FIFO?
complete flag
Valid data
USB function
Yes
ACK
NACK
No
Interrupt request
Interrupt request
Clear EP0i transmission
Write 1 to EP0i packet
(TRG.EP0i PKTE = 1)
End of control transfer
Clear EP0i transfer
(IFR0.EP0i TR = 0)
(IFR0.EP0i TS = 0)
complete flag
Application
request flag
enable bit