DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 119

MCU 5V 128K 100-TQFP

DF2345TE20

Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2345TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
4.2.3
The H8S/2345 Group enters the reset state when the RES pin goes low.
To ensure that the H8S/2345 Group is reset, hold the RES pin low for at least 20 ms at power-up.
To reset the H8S/2345 Group during operation, hold the RES pin low for at least 20 states.
When the RES pin goes high after being held low for the necessary time, the H8S/2345 Group
starts reset exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip supporting modules are
2. The reset exception handling vector address is read and transferred to the PC, and program
Figures 4.2 and 4.3 show examples of the reset sequence.
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
execution starts from the address indicated by the PC.
RES
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
(1) Reset exception handling vector address ((1) = H'0000)
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2))
(4) First program instruction
Reset Sequence
Figure 4.2 Reset Sequence (Modes 2 and 3)
Vector
fetch
(1)
(2)
Internal
processing
High
Rev. 4.00 Feb 15, 2006 page 93 of 900
Prefetch of first program
instruction
Section 4 Exception Handling
(3)
(4)
REJ09B0291-0400

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