DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 878

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Appendix B Internal I/O Register
TIOR1—Timer I/O Control Register 1
Bit
Initial value
Read/Write
Rev. 4.00 Feb 15, 2006 page 852 of 900
REJ09B0291-0400
:
:
:
TGR1B I/O Control
0
1
IOB3
R/W
7
0
0
1
0
1
0
1
0
1
0
1
*
IOB2
R/W
6
0
0
1
0
1
0
1
0
1
0
1
*
*
TGR1B
is output
compare
register
TGR1B
is input
capture
register
IOB1
R/W
5
0
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCB1 pin
Capture input
source is TGR0C
compare match/
input capture
IOB0
R/W
TGR1A I/O Control
4
0
0
1
0
1
0
1
IOA3
R/W
3
0
0
1
0
1
0
1
*
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
TGR0B compare match/input
capture
0
1
0
1
0
1
0
1
0
1
*
*
IOA2
TGR1A
is output
compare
register
TGR1A
is input
capture
register
R/W
2
0
H'FFE2
IOA1
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCA1 pin
Capture input
source is TGR0A
compare match/
input capture
R/W
1
0
*: Don’t care
IOA0
R/W
0
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
channel 0/TGR0A compare match/
input capture
*: Don’t care
TPU1