DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 299

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Port G Data Register (PGDR)
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Port G Register (PORTG)
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port G pins (PG
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G
read is performed while PGDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTG contents are determined by the pin
states, as PGDDR and PGDR are initialized. PORTG retains its prior state after a manual reset,
and in software standby mode.
Bit
Initial value
R/W
Bit
Initial value
R/W
Note: * Determined by state of pins PG
:
:
:
:
:
:
Undefined
Undefined
—
—
—
—
7
7
Undefined
Undefined
—
—
—
—
6
6
4
to PG
Undefined
Undefined
—
—
—
—
4
5
5
0
) must always be performed on PGDR.
to PG
PG4DR
0
.
PG4
R/W
—*
R
4
0
4
Rev. 4.00 Feb 15, 2006 page 273 of 900
PG3DR
R/W
PG3
—*
R
3
0
3
PG2DR
PG2
R/W
—*
R
2
0
2
PG1DR
Section 8 I/O Ports
REJ09B0291-0400
PG1
R/W
—*
R
1
0
1
PG0DR
4
PG0
R/W
—*
to PG
R
0
0
0
0
).