DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 21

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

15.2 Register Descriptions ........................................................................................................ 532
15.3 Operation .......................................................................................................................... 535
15.4 Usage Notes ...................................................................................................................... 536
Section 16 RAM
16.1 Overview........................................................................................................................... 537
16.2 Register Descriptions ........................................................................................................ 539
16.3 Operation .......................................................................................................................... 539
16.4 Usage Note........................................................................................................................ 539
Section 17 ROM
17.1 Overview........................................................................................................................... 541
17.2 Register Descriptions ........................................................................................................ 542
17.3 Operation .......................................................................................................................... 543
17.4 PROM Mode..................................................................................................................... 546
17.5 Programming..................................................................................................................... 549
17.6 Overview of Flash Memory .............................................................................................. 555
15.1.1 Features................................................................................................................ 529
15.1.2 Block Diagram ..................................................................................................... 530
15.1.3 Pin Configuration................................................................................................. 531
15.1.4 Register Configuration......................................................................................... 531
15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 532
15.2.2 D/A Control Register (DACR) ............................................................................ 532
15.2.3 Module Stop Control Register (MSTPCR) .......................................................... 534
16.1.1 Block Diagram ..................................................................................................... 538
16.1.2 Register Configuration......................................................................................... 538
16.2.1 System Control Register (SYSCR) ...................................................................... 539
17.1.1 Block Diagram ..................................................................................................... 541
17.1.2 Register Configuration......................................................................................... 542
17.2.1 Mode Control Register (MDCR) ......................................................................... 542
17.2.2 Bus Control Register L (BCRL) .......................................................................... 543
17.4.1 PROM Mode Setting............................................................................................ 546
17.4.2 Socket Adapter and Memory Map ....................................................................... 546
17.5.1 Overview.............................................................................................................. 549
17.5.2 Programming and Verification............................................................................. 549
17.5.3 Programming Precautions.................................................................................... 553
17.5.4 Reliability of Programmed Data .......................................................................... 554
17.6.1 Features................................................................................................................ 555
17.6.2 Block Diagram ..................................................................................................... 556
17.6.3 Flash Memory Operating Modes ......................................................................... 557
17.6.4 Pin Configuration................................................................................................. 562
.................................................................................................................. 537
.................................................................................................................. 541
Rev. 4.00 Feb 15, 2006 page xix of xxiv