DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 20

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

13.2 Register Descriptions ........................................................................................................ 481
13.3 Operation .......................................................................................................................... 486
13.4 Usage Note........................................................................................................................ 502
Section 14 A/D Converter
14.1 Overview........................................................................................................................... 507
14.2 Register Descriptions ........................................................................................................ 511
14.3 Interface to Bus Master ..................................................................................................... 516
14.4 Operation .......................................................................................................................... 517
14.5 Interrupts ........................................................................................................................... 523
14.6 Usage Notes ...................................................................................................................... 523
Section 15 D/A Converter
15.1 Overview........................................................................................................................... 529
Rev. 4.00 Feb 15, 2006 page xviii of xxiv
13.1.1 Features................................................................................................................ 477
13.1.2 Block Diagram ..................................................................................................... 478
13.1.3 Pin Configuration................................................................................................. 479
13.1.4 Register Configuration......................................................................................... 480
13.2.1 Smart Card Mode Register (SCMR) .................................................................... 481
13.2.2 Serial Status Register (SSR) ................................................................................ 482
13.2.3 Serial Mode Register (SMR)................................................................................ 484
13.2.4 Serial Control Register (SCR).............................................................................. 485
13.3.1 Overview.............................................................................................................. 486
13.3.2 Pin Connections ................................................................................................... 486
13.3.3 Data Format ......................................................................................................... 488
13.3.4 Register Settings .................................................................................................. 490
13.3.5 Clock.................................................................................................................... 492
13.3.6 Data Transfer Operations..................................................................................... 494
13.3.7 Operation in GSM Mode ..................................................................................... 501
14.1.1 Features................................................................................................................ 507
14.1.2 Block Diagram ..................................................................................................... 508
14.1.3 Pin Configuration................................................................................................. 509
14.1.4 Register Configuration......................................................................................... 510
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 511
14.2.2 A/D Control/Status Register (ADCSR) ............................................................... 512
14.2.3 A/D Control Register (ADCR) ............................................................................ 514
14.2.4 Module Stop Control Register (MSTPCR) .......................................................... 515
14.4.1 Single Mode (SCAN = 0) .................................................................................... 517
14.4.2 Scan Mode (SCAN = 1)....................................................................................... 519
14.4.3 Input Sampling and A/D Conversion Time ......................................................... 521
14.4.4 External Trigger Input Timing............................................................................. 522
................................................................................................. 507
................................................................................................. 529