DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 170
DF2345TE20
Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2345TE20V.pdf
(929 pages)
Specifications of DF2345TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20
HD64F2345TE20
Available stocks
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Quantity
Price
Company:
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
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Part Number:
DF2345TE20V
Manufacturer:
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Section 6 Bus Controller
Areas 1 to 6: In external expansion mode, all of areas 1 to 6 is external space.
When area 1 to 3 external space is accessed, the CS1 to CS3 pin signals respectively can be
output.
Only the basic bus interface can be used for areas 1 to 6.
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode,
the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip
RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the
RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes
external space.
Only the basic bus interface can be used for the area 7 memory interface.
6.3.5
Areas in Normal Mode (ZTAT, Mask ROM, and ROMless Versions Only)
In normal mode, a 64-kbyte address space comprising part of area 0 is controlled. Area
partitioning is not performed in normal mode. In ROM-disabled expansion mode, the space
excluding the on-chip RAM and internal I/O registers is external space. In ROM-enabled
expansion mode the space excluding the on-chip ROM, on-chip RAM, and internal I/O registers is
external space. The on-chip RAM is enabled when the RAME bit in the system control register
(SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the
corresponding space becomes external space .
When external space is accessed, the CS0 signal can be output.
The basic bus interface or burst ROM interface can be selected.
Rev. 4.00 Feb 15, 2006 page 144 of 900
REJ09B0291-0400
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