DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 234

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 8 I/O Ports
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Port 1 Data Register (P1DR)
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P1
P1DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Port 1 Register (PORT1)
PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 1 pins (P1
If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1
read is performed while P1DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT1 contents are determined by the pin
states, as P1DDR and P1DR are initialized. PORT1 retains its prior state after a manual reset, and
in software standby mode.
Rev. 4.00 Feb 15, 2006 page 208 of 900
REJ09B0291-0400
Bit
Initial value
R/W
Bit
Initial value
R/W
Note: * Determined by state of pins P1
Modes 2, 3, 6, and 7 are not available on the ROMless version.
:
:
:
:
:
:
P17DR
R/W
P17
—*
R
7
7
0
P16DR
R/W
P16
—*
R
6
6
0
7
to P1
P15DR
R/W
P15
0
—*
) must always be performed on P1DR.
7
R
5
5
0
to P1
0
P14DR
.
R/W
P14
—*
R
4
4
0
P13DR
R/W
P13
—*
R
3
3
0
P12DR
R/W
P12
—*
R
2
2
0
P11DR
R/W
P11
—*
R
1
1
0
7
P10DR
to P1
R/W
P10
—*
R
0
0
0
0
).