DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 601

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the H8S/2345 MCU measures the low period of the asynchronous
SCI communication data (H'00) transmitted continuously from the host, see figure 17.17. The SCI
transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The MCU
calculates the bit rate of the transmission from the host from the measured low period, and
transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should
confirm that this adjustment end indication (H'00) has been received normally, and transmit one
H'55 byte to the MCU. If reception cannot be performed normally, initiate boot mode again
(reset), and repeat the above operations. Depending on the host’s transmission bit rate and the
MCU’s system clock frequency, there will be a discrepancy between the bit rates of the host and
the MCU. To ensure correct SCI operation, the host’s transfer bit rate should be set to (4800, or
9600) bps.
Table 17.15 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the MCU’s bit rate is possible. The boot program should be executed within this
system clock range.
Table 17.15 System Clock Frequencies for which Automatic Adjustment of H8S/2345 Bit
On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2 kbytes area from H'FFEC00
to H'FFF3FF is reserved for use by the boot program, as shown in figure 17.18. The area to which
the programming control program is transferred is H'FFF400 to H'FFFBFF. The boot program
area can be used when the programming control program transferred into RAM enters the
execution state. A stack area should be set up as required.
Host Bit Rate
9600 bps
4800 bps
Figure 17.17 Measurement of Low Period of Host Transmission Data
Rate is Possible
Start
bit
D0
System Clock Frequency for which Automatic Adjustment
of H8S/2345 Bit Rate is Possible
8 MHz to 20 MHz
4 MHz to 20 MHz
Low period (9 bits) measured (H'00 data)
D1
D2
D3
D4
Rev. 4.00 Feb 15, 2006 page 575 of 900
D5
D6
D7
(1 or more bits)
REJ09B0291-0400
Section 17 ROM
High period
Stop
bit