DF2166VTE33 Renesas Electronics America, DF2166VTE33 Datasheet - Page 400

• Manufacturer Part Number: DF2166VTE33
• Description: MCU FLASH 3V 512K 33MHZ 144TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Rev. 3.00, 03/04, page 358 of 830
Bit
7
6
5
4
3
2
Bit Name
C/A
CHR
PE
O/E
STOP
MP
Initial Value
0
0
0
0
0
0
R/W Description
R/W Communication Mode
R/W Character Length (enabled only in asynchronous
R/W Parity Enable (enabled only in asynchronous mode)
R/W Parity Mode (enabled only when the PE bit is 1 in
R/W Stop Bit Length (enabled only in asynchronous mode)
R/W Multiprocessor Mode (enabled only in asynchronous
0: Asynchronous mode
1: Clock synchronous mode
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is fixed
In clock synchronous mode, a fixed data length of 8
bits is used.
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. For a multiprocessor format,
parity bit addition and checking are not performed
regardless of the PE bit setting.
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the
next transmit frame.
mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and
O/E bit settings are invalid in multiprocessor mode.
and the MSB of TDR is not transmitted in
transmission.