HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 204

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Exception Handling
• DMA Address error
4.5.3
1. NMI
2. IRL Interrupts
3. IRQ Pin Interrupts
Rev.6.00 Mar. 27, 2009 Page 146 of 1036
REJ09B0254-0600
⎯ Conditions:
⎯ Operations: The PC of the instruction immediately after the instruction executed before the
Conditions: NMI pin edge detection
Operations: The PC and SR after the instruction that receives the interrupt are saved to the SPC
and SSR, respectively. H'1C0 is set to INTEVT and INTEVT2. The BL, MD, and RB bits of
the SR are set to 1 and a branch occurs to PC = VBR + H'0600. This interrupt is not masked by
SR.IMASK and received with top priority when the SR’s BL bit in SR is 0. When the BL bit is
1, the interrupt is masked. See section 7, Interrupt Controller (INTC), for more information.
Conditions: The value of the interrupt mask bits in SR is lower than the IRL3 to IRL0 level
and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC value after the instruction at which the interrupt is accepted is saved to the
SPC. SR at the time the interrupt is accepted is saved to SSR. The code corresponding to the
IRL3 to IRL0 level is set in INTEVT and INTEVT2. The corresponding code is given as
H'200 + [IRL3 to IRL0] × H'20. See table 7.5, for the corresponding codes. The BL, MD, and
RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not set
in SR.IMASK. See section 7, Interrupt Controller (INTC), for more information.
Conditions: IRQ pin is asserted and SR.IMASK is lower than the IRQ priority level and the
BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC value after the instruction at which the interrupt is accepted is saved to the
SPC. The SR at the point the interrupt is accepted is saved to the SSR. The code corresponding
to the interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR
are set to 1 and a branch occurs to VBR + H'0600. The received level is not set to SR.IMASK.
See section 7, Interrupt Controller (INTC), for more information.
a. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
b. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
exception occurs is saved to the SPC. SR when the exception occurs is saved to SSR.
H'5C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs
to PC = VBR + H'0100.
Interrupts
4n + 3)