HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 599

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The reception margin in the asynchronous mode is given by formula 1.
Formula 1:
Where:
Assuming values of F = 0, D = 0.5 and N = 372 in formula (1), the reception margin is given by
formula 2.
Formula 2:
This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%.
Cautions for Clock Synchronous External Clock Mode:
• Set TE = RE = 1 only when the external clock SCK0 is 1.
• Do not set TE = RE = 1 until at least four clocks after the external clock SCK0 has changed
• When receiving, RDRF is 1 when RE is set to zero 2.5 to 3.5 clocks after the rising edge of the
Caution for Clock Synchronous Internal Clock Mode: When receiving, RDRF is 1 when RE is
set to zero 1.5 clocks after the rising edge of the SCK0 output of the D7 bit in RxD0, but it cannot
be copied to SCRDR.
from 0 to 1.
SCK0 input of the D7 bit in RxD0, but it cannot be copied to SCRDR.
M = 0.5 −
M = (0.5 – 1/(2 × 16)) × 100%
M = Reception margin (%)
N = Ratio of clock frequency to bit rate (N = 16)
D = Clock duty cycle (D = 0–1.0)
L = Frame length (L = 9–12)
F = Absolute deviation of clock frequency
= 46.875%
2N
1
− (L − 0.5)F −
D − 0.5
N
(1 + F) × 100%
Section 17 Serial Communication Interface (SCI)
Rev.6.00 Mar. 27, 2009 Page 541 of 1036
REJ09B0254-0600