HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 37

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

31.3 Register Descriptions ........................................................................................................ 916
31.4 H-UDI Operations............................................................................................................. 925
31.5 Usage Notes ...................................................................................................................... 928
31.6 Advanced User Debugger (AUD) ..................................................................................... 928
Section 32 Electrical Characteristics
32.1 Absolute Maximum Ratings ............................................................................................. 929
32.2 DC Characteristics ............................................................................................................ 931
32.3 AC Characteristics ............................................................................................................ 934
32.4 A/D Converter Characteristics .......................................................................................... 991
32.5 D/A Converter Characteristics .......................................................................................... 991
Appendix A Pin Functions
A.1
A.2
31.2.1 Pin Description .................................................................................................... 915
31.2.2 Block Diagram..................................................................................................... 916
31.3.1 Bypass Register (SDBPR) ................................................................................... 917
31.3.2 Instruction Register (SDIR) ................................................................................. 917
31.3.3 Boundary-Scan Register (SDBSR) ...................................................................... 918
31.4.1 TAP Controller .................................................................................................... 925
31.4.2 Reset Configuration ............................................................................................. 926
31.4.3 H-UDI Reset ........................................................................................................ 927
31.4.4 H-UDI Interrupt ................................................................................................... 927
31.4.5 Bypass.................................................................................................................. 927
31.4.6 Using H-UDI to Recover from Sleep Mode......................................................... 927
32.3.1 Clock Timing ....................................................................................................... 937
32.3.2 Control Signal Timing ......................................................................................... 946
32.3.3 AC Bus Timing.................................................................................................... 949
32.3.4 Basic Timing........................................................................................................ 951
32.3.5 Burst ROM Timing .............................................................................................. 954
32.3.6 Synchronous DRAM Timing ............................................................................... 957
32.3.7 PCMCIA Timing ................................................................................................. 968
32.3.8 Peripheral Module Signal Timing........................................................................ 975
32.3.9 H-UDI-Related Pin Timing.................................................................................. 978
32.3.10 LCDC Timing ...................................................................................................... 980
32.3.11 SIOF Module Signal Timing................................................................................ 982
32.3.12 USB Module Signal Timing ................................................................................ 985
32.3.13 AFEIF Module Signal Timing ............................................................................. 987
32.3.14 AC Characteristics Measurement Conditions ...................................................... 989
32.3.15 Delay Time Variation Due to Load Capacitance ................................................. 990
Pin Functions .................................................................................................................... 993
Treatment of Unused Pins................................................................................................. 999
................................................................................................ 993
.............................................................................. 929
Rev.6.00 Mar. 27, 2009 Page xxxv of lvi
REJ09B0254-0600