HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 780

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 USB Function Controller
23.9
23.9.1
Note the following for EPDR0s that receives 8-byte setup data:
1. As a latest setup command must be received in high priority, the write from the USB bus takes
2. EPDR0s must always be read in 8-byte units. If the read is terminated at a midpoint, the data
23.9.2
If a USB cable is disconnected during data transfer, the data being received or transmitted may
remain in the FIFO. When disconnecting a USB cable, clear the FIFO.
While a FIFO is transferring data, it must not be cleared.
23.9.3
Note the following when reading or writing to a data register of this module.
(1) Receive data registers
The receive data registers must not be read exceeding the valid amount of receive data, that is, the
number of bytes indicated by the receive data size register. Even for EPDR1 which has double
FIFO buffers, the maximum data to be read at one time is 64 bytes. After the data is read from the
current valid FIFO buffer, be sure to write 1 to EP1RDFN in TRG, which switches the valid
buffer, updates the receive data size to the new number of bytes, and enables the next data to be
received.
(2) Transmit data registers
The transmit data registers must not be written to exceeding the maximum packet size. Even for
EPDR2 which has double FIFO buffers, write data within the maximum packet size at one time.
After the data is written, write 1 to PKTE in TRG to switch the valid buffer and enable the next
data to be written. Data must not be continuously written to the two FIFO buffers.
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REJ09B0254-0600
priority over the read from the CPU. If the next setup command reception is started while the
CPU is reading data after the data is received, the read from the CPU is forcibly terminated.
Therefore, the data read after reception is started becomes invalid.
received at the next setup cannot be read correctly.
Usage Notes
Receiving Setup Data
Clearing the FIFO
Overreading and Overwriting the Data Registers