UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 263
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3737GF-GAS-AX
Manufacturer Part Number
UPD70F3737GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3737GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3737GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(c) Notes on rewriting TPnCCR0 register
When rewriting the value of the TPnCCR0 register to a smaller value, stop counting first and then change
the set value.
If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
Remarks 1. Interval time (1): (D
If the value of the TPnCCR0 register is changed from D
but less than D
register has been rewritten. Consequently, the value that is compared with the 16-bit counter value is D
Because the counter value has already exceeded D
overflows, and then counts up again from 0000H. When the counter value matches D
signal is generated and the output of the TOPn0 pin is inverted.
Therefore, the INTTPnCC0 signal may not be generated at the interval “(D
“(D
“(10000H + D
2
(CCR0 buffer register)
+ 1) × Count clock cycle” as originally expected, but instead may be generated at an interval of
INTTPnCC0 signal
TPnCCR0 register
TOPn0 pin output
2. n = 0 to 5
16-bit counter
TPnOL0 bit
2
Interval time (NG): (10000H + D
Interval time (2): (D
TPnCE bit
+ 1) × Count clock cycle”.
1
, the TPnCCR0 register value is transferred to the CCR0 buffer register as soon as the
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Figure 7-12. Rewriting TPnCCR0 Register
L
Interval time (1)
1
2
User’s Manual U18953EJ5V0UD
+ 1) × Count clock cycle
+ 1) × Count clock cycle
D
1
D
1
2
+ 1) × Count clock cycle
D
2
Interval time (NG)
2
, however, the 16-bit counter counts up to FFFFH,
D
1
1
to D
2
while the counter value is greater than D
D
2
D
2
Interval
time (2)
1
D
+ 1) × Count clock cycle” or
2
2
, the INTTPnCC0
261
2
.
2
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