UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 775
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UPD70F3737GF-GAS-AX
Manufacturer Part Number
UPD70F3737GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3737GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
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Company:
Part Number:
UPD70F3737GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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20.10 DMA Abort Factors
memory/on-chip peripheral I/O.
20.11 End of DMA Transfer
bit is cleared to 0 and TCn bit is set to 1, a DMA transfer end interrupt request signal (INTDMAn) is generated for the
interrupt controller (INTC) (n = 0 to 3).
DMA transfer by using the DMA transfer end interrupt or polling the TCn bit.
20.12 Operation Timing
DMA transfer is aborted if a bus hold occurs.
The same applies if transfer is executed between the internal memory/on-chip peripheral I/O and internal
When the bus hold is cleared, DMA transfer is resumed.
When DMA transfer has been completed the number of times set to the DBCn register and when the DCHCn.Enn
The V850ES/JG3-L does not output a terminal count signal to an external device. Therefore, confirm completion of
The operation timing of DMA is as follows.
Four examples are shown:
• Multiple channels request DMA transfer simultaneously (see Figure 20-4).
• A new DMA transfer with a higher priority is requested during a DMA transfer (see Figure 20-5).
• A new DMA transfer request for the same channel is ignored (one channel) (see Figure 20-6).
• A new DMA transfer request for the same channel is ignored (multiple channels) (see Figure 20-7).
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
User’s Manual U18953EJ5V0UD
773
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